Coarse Tune (G_CT) Design

[ Back-to-Back Varactor Diodes ] Since the varactor's capacitance value does not change linearly with bias voltage, we may need to choose different varactor diodes, and then put them back-to-back (Fig.9) to make our VCO tuning more linear. In this project, we are using the same varactor diodes. These back-to-back varactor diodes serve as Coarse Tune.

Fig.13 Shows the Re[Z_CT] (in blue) and Im[Z_CT] (in red) at different bias voltages.

We now want to match the LHS curve with our Coarse Tune Network. At high V_CT (for example, -19V) the coarse tune f_H should match the base f_H. When we say match, we mean that the negative base admittance -Y_J curve will coincide the coarse tune admittance Y_CT curve at the desired f_H. This intersection is the oscillation frequency. Similarly, when we plot the Y_CT curves of V_CT=-8V, and V_CT=-2V, we expect that they will coincide at f_M and f_L, respectively. These are shown in Fig.15 below.

To better understand what is happening, let's put the figure in rectangular coordinates. Again, remember the admittance Y_LHS curve is made negative. Our goal is to make the matching network to meet the following requirements:

1^st, -Re[Y_LHS] must be greater than Re[Y_CT] throughout the frequency range.

Re[Y_CT] = 0.8(-Re[Y_LHS]) is recommended.

2^nd, the intersection of -Im[Y_LHS] and -1.0V (the lowest-voltage) Im[Y_CT] must cross below f_L, and, the intersection of -Im[Y_LHS] and -19.0V (the highest-voltage) Im[Y_CT] must cross beyond f_H.

3^rd, flat curves of real parts are preferred.

4^th, straight lines of imaginary parts are preferred

Basically, Z₀₄ (Fig.16) can be achieved by using some length and width of transmission lines, in which, some l/4 transformation lines may be needed. In order to lower phase noise, adding an additional l/2 transmission line is recommended. However, this might shrink the tuning range.

After choosing Z₀₄ to be a 51mil wide, 275mil long transmission line, we have our design (shown in Fig.19a and Fig.19b) from Serenade^®

Fig.19a Coarse Tune Matching Simulation from Serenade

Fig.19b Coarse Tune Matching Simulation from Serenade

( -Y_LHS and Y_CT at V_CT=-2V, -8V, and -19V)

| Introduction | Measurements | Fundamental Theory | Transistor Selection |

| Terminating Network Design | Load Network Design | Coarse Tune Design |

| DC Bias Circuit Design | Fine Tune Design | Phase Noise |

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